The present technology relates to an information processor and control method of the same, and more particularly, to an information processor adapted to operate in synchronism with a clock signal and control method of the same.
A circuit adapted to operate in synchronism with a clock signal has a storage element and processing circuit. The storage element is, for example, a register that holds and outputs a data signal in synchronism with the clock signal. The processing circuit includes a combinational logic circuit adapted to perform logic operations or the like on the output data signal. If the output of an execution result from the processing circuit is synchronized with the clock signal in such a circuit, a retiming circuit may be further provided to adjust the output timing. For example, a retiming circuit has been proposed that includes a flip-flop adapted to hold and output an input signal in synchronism with a clock signal (refer to Japanese Patent Laid-Open No. 2009-290775).
Such a retiming circuit may hold the execution result of an operation on a data signal at a timing (e.g., negative edge) different from a timing (e.g., positive edge) at which the data signal is output to the processing circuit. Delaying the timing at which to hold the execution result from the timing at which to output the data signal to the processing circuit makes the execution result be held unfailingly, thereby suppressing the occurrences of timing errors in the retiming circuit.